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DMA Write with Pipeline Stall
When a memDMA, ADC DMA or SPORT DMA is active, a DMA failure may occur if a pipeline stall coincides with DMA write activity. As a result, all DMA activity will be halted. Pipeline stalls could happen for the following reasons:
a. Core IO read/writes (e.g. “AX0 = IO(0x300);”)
b. Direct Core accesses to EMI - especially for reads.
Фактически это запрещает (для большинства задач) вообще использование фоновых DMA (кроме SPI). В 219x это устранено с ревизии 1.0. Неужели в 2199х это так и есть???
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